The present invention relates to a semiconductor memory device, and more particularly to a data input/output device for a semiconductor memory device provided with a delay circuit for synchronizing in timing between a clock signal and a data stroboscopic signals and data signals.
As the high speed performance of the computer system has been improved, the high speed performance of the semiconductor memory device depends upon the data transfer rate. There was proposed a double data rate for conducting two times data input/output operations in one clock in order to improve the data transfer rate. FIG. 1 is a timing chart illustrative of waveforms of double data rate operations static random access memory. Data stroboscopic signals (DQS) and data signals (DQ) are outputted in synchronizing with rising edge of clock signal (CLK) and reversed phase clock signal (CLBK), so that two times of the data input and output operations are conducted in one clock. In order to realize the double data rate, there are used a clock synchronizing circuit with a feed-back system such as a phase-locked loop and a delay-locked loop, and a clock synchronizing circuit with a sequence control system such as a synchronous mirror delay as disclosed in Japanese laid-open patent publication No. 8-237091 and a clock supplying semiconductor circuit as disclosed in Japanese laid-open patent publication No. 9-152656.
FIG. 2 is a block diagram illustrative of a circuit configuration of a digital delay-locked loop circuit. The clock signal CLK and the reversed phase clock signal CLKB are inputted into two input terminals. First and second output enable signal generator systems 500 and 510 are provided, each of which is connected to the two input terminals individually. The first and second output enable signal generator systems 500 and 510 generate output enable signals 1 and 2 respectively on the basis of the inputs of the clock signal CLK and the reversed phase clock signal CLKB. An output circuit 520 is provided which is connected to the individual output terminals of the first and second output enable signal generator systems 500 and 510. The output circuit 520 receives the output enable signals 1 and 2 from the first and second output enable signal generator systems 500 and 510 so that the output circuit 520 generates a data signal DQ or a data stroboscopic signal SQS in accordance with the output enable signals 1 and 2 and internal data. An end circuit 530 is provided which is connected to the output circuit 520 for receiving the data signal DO or the data stroboscopic signal SQS from the output circuit 520 so that the end circuit 530 generates a signal necessary for access measurement on the basis of the data signal DQ or the data stroboscopic signal SQS. Each of the first and second output enable signal generator systems 500 and 510 has an input first stage circuit 501 which is connected to the two input terminals for receiving the clock signal CLK and the reversed phase clock s:. Each of the first and second output enable signal generator systems 500 and 510 also has a delay circuit alignment 502 connected to the input first stage circuit 501 for receiving an output signal from the input first stage circuit 501 for delaying the output signal. Each of the first and second output enable signal generator systems 500 and 510 also has a buffering circuit 506 which is connected to the delay circuit alignment 502 for receiving an output signal from the delay circuit alignment 502. Each of the first and second output enable signal generator systems 500 and 510 also has a delay device 505 which is connected to the delay circuit alignment 502 for delaying the output signal from the delay circuit alignment 502 in consideration of the delay times of the input first stage circuit 501, the buffering circuit 506, the output circuit 520, and the end circuit 530. The delay device 505 delays the output signal 4 from the delay circuit alignment 502 to generate a delayed output signal 5. Each of the first and second output enable signal generator systems 500 and 510 also has a phase comparator 503 which has two inputs connected to the output of the input first stage circuit 501 for receiving the output signal 3 from the input first stage circuit 501 and also receiving the output signal 5 from the delay device 505, so that the phase comparator 503 compares phases between the output signals 3 and 5. Each of the first and second output enable signal generator systems 500 and 510 also has a control circuit 504 which is connected to the phase comparator 503 for receiving an output from the phase comparator 503 to generate a control signal on the basis of the output signal from the phase comparator 503. The control circuit 504 is also connected to the delay circuit alignment 502 to send the control signal to the delay circuit alignment 502 for controlling the delay of the delay circuit alignment 502. The first and second output enable signal generator systems 500 and 510 are different only in operations in reversed phases to each other.
FIG. 3 is a timing chart illustrative of waveforms in operations of the delay-locked loop circuit of FIG. 2. "t0" is a delay time defined from a cross point of a rising or falling edge of the clock signal (CLK) and the reversed phase clock signal (CLKB) to a rising edge of the output signal 3 from the input first stage circuit 501. "t1" is a delay time defined from a rising edge of the output enable signals 1 and 2 of the output circuit 520 to an access measurement point of the end circuit 530. "t2" is a delay time defined from the rising edge of the reference signal 4 to the rising edge of the output enable signal. "t5" is a delay time of the delay device 505.
The delay time "t5" of the delay device 505 is given by the following equation. EQU t5=(t0+t1+t2) (1)
Skew tAC and tDQSCK of he clock signal CLK or the reversed phase clock signal CLKB and the data signal DQ and the data stroboscopic signal DQS are adjusted to the following regulation. The delay device 505 delays in a total amount of individual delay times of the input first stage circuit 501, the output circuit 520, the end circuit 530 and the buffering circuit 506, so that a timing synchronizing between the output signals 3 and 5 is made by the phase comparator 503 and the control circuit 504.
FIG. 4 is a block diagram illustrative of a clock supplying semiconductor circuit. FIG. 5 is a timing chart illustrative of waveforms of a clock supplying semiconductor circuit of FIG. 4 An output enable signal generating system 700 has an input first state circuit 501, control circuits 710 and 780, delay circuit alignments 760 and 790 and pulse generator circuits 770 and 800. The output enable signal generating system 700 generates an output enable signal 1 which is to be inputted into the input circuit 520. An output enable signal generating system 810 has the same circuit configuration as the output enable signal generating system 700. The output enable signal generating system 810 generates an output enable signal 2 which is to be inputted into the input circuit 520. The end circuit 530 is connected to the output terminal o the output circuit 520. The delay circuit alignment 760 has four delay circuits 720, 730, 740 and 750. There are provided two flip-flop circuits 702 and 711, two AND-gates 712 and 773. The pulse generator circuit 770 has a delay circuit 771. There are provided three inverters 701, 703 and 705. A delay device 704 is further provided for timing synchronization of the clock supply semiconductor circuit.
A delay time "t6" of the delay device 704 is defined to be represented by the following equation. EQU t6=(t0+t1+t2+t3.times.2) (2)
Skew tAC and tDQSCK of he clock signal CLK or the reversed phase clock signal CLKB and the data signal DQ and the data stroboscopic signal DQS are adjusted to the following regulation. "t3" is a delay time defined from a rising edge of the output signal 3 from the input first stage circuit 501 to either a falling edge of a return signal 7 or a rising edge of a return signal 6 of a delay chain of the clock supply semiconductor circuit.
In the static random access memory operable in double data rate, tAC and tDQSCK are .+-.0.1.times.tCK. If the clock frequency tCK of the clock signal CLK is 10 nanoseconds or 100 MHz, then tAC=.+-.1 nanosecond. This regulation includes variations of output, voltage, and temperature and variations caused in manufacturing processes, for which reason it is important to do a highly accurate adjustment to the delay times "t5" and "t6" of the delay devices 505 and 704. FIG. 6A is a circuit diagram illustrative of a first conventional circuit configuration of a delay device. Each of the delay devices 505 and 704 may has a circuit configuration of an inverter chain as shown in FIG. 6A, wherein a plurality of inverters 1200, 1201, 1202 and 1203 are connected in series to form a multi-stage inverter chain so that the delay time corresponds to the delay time "t5" or "t6". FIG. 6B is a circuit diagram illustrative of a second conventional circuit configuration of a delay device. Alternatively, each of the delay devices 505 and 704 may has another circuit configuration of an inverter chain connected with capacitors as shown in FIG. 6B, wherein a plurality of inverters 1204, 1205, 1206 and 1207 are connected in series to form a multi-stage inverter chain and capacitors 1208 and 1209 are connected to the multi-stage inverter chain. Still another method for adjusting the delay time is to adjust a transistor size.
If the delay devices 505 and 704 comprise the above multi-stage inverter chains, then a problem is raised with an enlargement of error due to variations in voltage, temperature and manufacturing variation. Particularly, in the above equations (1) and (2), the delay times "t2" and "t3" are caused by the logic devices, for which reason it is not so difficult to adjust the delay time. However, the delay times "t5" and "t6" include the delay time "t0+ti" which are caused by the non-logic circuits, for which reason the errors may become remarkable.
The output circuit 520 has the following problem. There may be raised variations in power ratio between p-channel and n-channel MOS field effect transistors as the output transistors, whereby the delay times of the output circuit are different between in high level output and low level output. Therefore, it is difficult to adjust the delay time of the output circuit because the delay time of the output circuit largely depends upon the delay times of the output transistors. In the input first stage circuit, high and low levels of the clock signal CLK and the reversed phase clock signal CLKB are set about 1.6V and 0.9V respectively in accordance with the SSTL2 regulation. In consideration of the variations in the conditions of the conventional circuit configuration, it is difficult to adjust the delay time.
In the above circumstances, it had been required to develop a novel semiconductor memory device free from the above problem.